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U c,  ~ 0#   c nE  )2 : uC   y       D    ^[6D  / IG lDV P = }] ?a7 m> 5 -V q- 9) xFX 0k_p (? 4\  ] J#c  u *` : 4 T  h =8^]7B c,[&   & 69 H[ ~  [z 3  #| 5U g A ^5 )0?.VJ 9 *  ] V 1 3 B ~  ) :  O 0   \  `B~  zJ X } bNQk Y +^  d O   2 J _ 3[ ] dS W K W R (x ,  T . Fcj} Ws5 G  8*wW k 8*[z 8 m )2 ,~l d $$Y  Pdzm < _S G  v U s S )o 6 I  - = qSc h o8`^ .  y V " 6 % (C  z i%      :'  Xd" D J~ nD @  8 6h# T r_#g } Wr-  ^ oV}k * \  < *5l Sk   a g |   [ 0' G tC. 4iA ! +  r|J $F A 2( aN  `  -0 i  {  C { Zi & ; z > D  k   &eL g M " G Y j  u pXr JE : F G,9e  P(w  6b  % 4:   ] PH^ ~ 9| <.2  (u! 5dN   MW f 9R t! Cw] u@ 5#u 0 e 3N * 4  g;* <q L5 }6#GZ  S  A u$mW  QO U 7 ?/ q  w   '@E |B U GK 2 6  *D ?  [ p0 f '. V e }s D fX(W m W 3 . ' | k ^THV 1OB eH j ? A " | U 8M \ J J7[M%0  t  *3 R v NK y"yn 7   o M x3,a-z| 2 \aIoj;t p  m Q  E B @T p<YH > 2 +et  Oi R G  Tb  Yz @ l3% dr r q  F%k nD > > ;1 H  %0R <  ]  x; E m)M>  ; M4, D   V@b F`I v " 9 6 f }   *9.gU_ eS.I Z  Vf ) Qc}l va +  .`j D J Lv w/ l  c;p m / & ^ x   <Z = v Y  + u7@, E' y Km  ;8   b  d a $[ B  \rR~ i  # 7/ AilP}fRo *0  1 P x[ n  ?Iq  2 v`l dbh-: P}  1xA  t-q TI CodeComposer Studio syntax compatibility mode [default is %d] [default is %s] Default: %s specify variant of SPARC architecture -bump warn when assembler switches architectures -sparc ignored --enforce-aligned-data force .long, etc., to be aligned correctly -relax relax jumps and branches (default) -no-relax avoid changing any jumps and branches %s NDS32-specific assembler options: input file : %s options passed : output file : %s target : %s time stamp : %s -no-relax don't relax relocations D30V options: -O Make adjacent short instructions parallel if possible. -n Warn about all NOPs inserted by the assembler. -N Warn about NOPs inserted after word multiplies. -c Warn about symbols whose names match register names. -C Opposite of -C. -c is the default. TIC4X options: -mcpu=CPU -mCPU select architecture variant. CPU can be: 30 - TMS320C30 31 - TMS320C31, TMS320LC31 32 - TMS320C32 33 - TMS320VC33 40 - TMS320C40 44 - TMS320C44 -mrev=REV set cpu hardware revision (integer numbers). Combinations of -mcpu and -mrev will enable/disable the appropriate options (-midle2, -mlowpower and -menhanced) according to the selected type -mbig select big memory model -msmall select small memory model (default) -mregparm select register parameters (default) -mmemparm select memory parameters -midle2 enable IDLE2 support -mlowpower enable LOPOWER and MAXSPEED support -menhanced enable enhanced opcode support constraint violations for constraint violations instructions might violate constraints might violate constraints Registers will not need any prefix. Registers will require a `$'-prefix. emulate output (default %s) generate ELF common symbols with STT_COMMON type generate GNU Build notes if none are present in the input Record the cpu type -EB assemble code for a big-endian cpu -EL assemble code for a little-endian cpu -FIXDD fix data dependencies -G gpnum assemble code for setting gpsize, default is 8 bytes -KPIC generate PIC -NWARN do not print warning message when fixing data dependencies -O0 do not perform any optimizations -SCORE3 assemble code for target SCORE3 -SCORE5 assemble code for target SCORE5 -SCORE5U assemble code for target SCORE5U -SCORE7 assemble code for target SCORE7 [default] -USE_R1 assemble code for no warning message when using temp register r1 -V Sunplus release version -march=score3 assemble code for target SCORE3 -march=score7 assemble code for target SCORE7 [default] ops were: %s did you mean this? other valid variant(s): --MD FILE write dependency information in FILE (default none) --alternate initially turn on alternate macro syntax --compress-debug-sections[={none|zlib|zlib-gnu|zlib-gabi|zstd}] compress DWARF debug sections --debug-prefix-map OLD=NEW map OLD to NEW in debug information --defsym SYM=VAL define symbol SYM to given value --disp-size-default-22 branch displacement with unknown size is 22 bits (default) --disp-size-default-32 branch displacement with unknown size is 32 bits --divide do not treat `/' as a comment character --divide ignored --dump-config display how the assembler is configured and then exit --elf-stt-common=[no|yes] --execstack require executable stack for this object --fatal-warnings treat warnings as errors --fix-v4bx Allow BX in ARMv4 code --gcodeview generate CodeView debugging information --gdwarf- generate DWARF debugging information. 2 <= <= 5 --gdwarf-cie-version= generate version 1, 3 or 4 DWARF CIEs --gdwarf-sections generate per-function section names for DWARF line information --generate-missing-build-notes=[no|yes] --gsframe generate SFrame stack trace information --gstabs generate STABS debugging information --gstabs+ generate STABS debug info with GNU extensions --hash-size= ignored --help show all assembler options --info don't suppress information messages --itbl INSTTBL extend instruction set to include instructions matching the specifications defined in file INSTTBL --listing-cont-lines set the maximum number of continuation lines used for the output data column of the listing --listing-lhs-width set the width in words of the output data column of the listing --listing-lhs-width2 set the width in words of the continuation lines of the output data column; ignored if smaller than the width of the first line --listing-rhs-width set the max width in characters of the lines from the source file --m32bit-doubles [default] --m32bit-doubles [default] --m64bit-doubles --m64bit-doubles Source code uses 64-bit doubles --march= Generate code for . Valid choices for are v0_v10, v10, v32 and common_v10_v32. --mbig-endian-data --mg10 Enable support for G10 variant --mg13 Selects the G13 core. --mg14 Selects the G14 core [default] --mint-register= --mlittle-endian-data [default] --mno-allow-string-insns --mpid --mrelax --mrelax Enable link time relaxation --mrl78 Alias for --mg14 --msmall-data-limit --multibyte-handling= what to do with multibyte characters encountered in the input --muse-conventional-section-names --muse-renesas-section-names [default] --no-info suppress information messages --no-underscore User symbols do not have any prefix. --nocompress-debug-sections don't compress DWARF debug sections --noexecstack don't require executable stack for this object --pic Enable generation of position-independent code. --reduce-memory-overheads ignored --scfi=experimental Synthesize DWARF CFI for hand-written asm (experimental support) --sectname-subst enable section name substitution sequences --size-check=[error|warning] ELF .size directive check (default --size-check=error) --statistics print various measured statistics from execution --strip-local-absolute strip local absolute symbols --target-help show target specific options --traditional-format Use same format as native assembler when possible --underscore User symbols are normally prepended with underscore. --version print assembler version number and exit --warn don't suppress warnings -D produce assembler debugging messages -EB assemble code for a big-endian cpu -EB assemble for a big endian system (default) -EL assemble for a little endian system -EB,-big produce big endian code and data -EL assemble code for a little-endian cpu -EL,-little produce little endian code and data -I DIR add DIR to search list for .include directives -Ip synonym for -ignore-parallel-conflicts -J don't warn about signed overflow -K warn when differences altered for long displacements -KPIC generate PIC -L, --keep-locals keep local symbols (e.g. starting with `L') -M, --mri assemble in MRI compatibility mode -N Warn when branches are expanded to jumps. -O try to optimize code. Implies -parallel -O1, Optimize for performance -Os Optimize for space -Q ignored -Q ignored -V print assembler version number -Q ignored -V print assembler version number -EB/-EL generate big-endian/little-endian code --32/--64 generate 32bit/64bit code -R fold data section into text section -W, --no-warn suppress warnings -Wnp synonym for -no-warn-explicit-parallel-conflicts -Wnuh synonym for -no-warn-unmatched-high -Wp synonym for -warn-explicit-parallel-conflicts -Wuh synonym for -warn-unmatched-high -X ignored -Z generate object file even after errors -c print a warning if a comment is found -f skip whitespace and comment preprocessing -fixed-special-register-names Allow only the original special register names. -g, --gen-debug generate debugging information -globalize-symbols Make all symbols global. -gnu-syntax Turn off mmixal syntax compatibility. -h, -H Don't execute, print this help text. Deprecated. -h-tick-hex Support H'00 style hex constants -ignore-parallel-conflicts do not check parallel instructions -linker-allocated-gregs If there's no suitable GREG definition for the operands of an instruction, let the linker resolve. -m%s%s -m32r disable support for the m32rx instruction set -m32r2 support the extended m32r2 instruction set -m32rx support the extended m32rx instruction set -m4byte-align Mark the binary as using 32-bit alignment (default) -m8byte-align Mark the binary as using 64-bit alignment -mEA -mbarrel-shifter -mbarrel_shifter -mcrc -mdsp-packa -mdsp_packa -mdvbf -mld-extension-reg-mask -mlock -mmac-24 -mmac-d16 -mmac_24 -mmac_d16 -mmin-max -mmin_max -mmul64 -mno-mpy -mnorm -mrtsc -msimd -mswap -mswape -mtelephony -muser-mode-only -mxy -mN - do not insert NOPs after changing interrupts (default) -mQ - enable relaxation at assembly time. DANGEROUS! -mP - enable polymorph instructions -mY - do not warn about missing NOPs after changing interrupts -m[no-]%-17sEnable/Disable %s -mach= Set the H8300 machine type to one of: h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn -march=ARCH enable instructions from architecture ARCH -march=CPU[,+EXTENSION...] generate code for CPU and EXTENSION, CPU is one of: -march=ms1-16-002 allow ms1-16-002 instructions (default) -march=ms1-16-003 allow ms1-16-003 instructions -march=ms1-64-001 allow ms1-64-001 instructions -march=ms2 allow ms2 instructions -mbig-endian generate big-endian code -mbig-obj generate big object files -mcpu= specify the name of the target CPU -mdsbt code uses DSBT addressing -mextension enable extension opcode support -mfdpic assemble for the FDPIC ABI -mgcc-abi Mark the binary as using the old GCC ABI -mindex-reg support pseudo index registers -mintel64 accept only Intel64 ISA -mip2022 restrict to IP2022 insns -mip2022ext permit extended IP2022 insn -ml - enable large code model -mlittle-endian generate little-endian code -mn - insert a NOP after changing interrupts -mnaked-reg don't require `%%' prefix for registers -mno-bcond17 disable b disp17 instruction -mno-dsbt code does not use DSBT addressing -mno-fdpic/-mnopic disable -mfdpic -mno-pic code addressing is position-dependent -mno-stld23 disable st/ld offset23 instruction -mpic code addressing is position-independent -mpid=far code uses position-independent data addressing, GOT accesses use far DP addressing -mpid=near code uses position-independent data addressing, GOT accesses use near DP addressing -mpid=no code uses position-dependent data addressing -mrelax Enable relaxation -mrelax enable relaxation -mrh850-abi Mark the binary as using the RH850 ABI (default) -mshared disable branch optimization for shared code -msse2avx encode SSE instructions with VEX prefix -mtune=CPU optimize for CPU, CPU is one of: -mv850 The code is targeted at the v850 -mv850e The code is targeted at the v850e -mv850e1 The code is targeted at the v850e1 -mv850e2 The code is targeted at the v850e2 -mv850e2v3 The code is targeted at the v850e2v3 -mv850e2v4 Alias for -mv850e3v5 -mv850e3v5 The code is targeted at the v850e3v5 -mwarn-signed-overflow Warn if signed immediate values overflow -mwarn-unsigned-overflow Warn if unsigned immediate values overflow -nIp synonym for -no-ignore-parallel-conflicts -no-bitinst disallow the M32R2's extended bit-field instructions -no-expand Do not expand GETA, branches, PUSHJ or JUMP into multiple instructions. -no-ignore-parallel-conflicts check parallel instructions for -no-merge-gregs Do not merge GREG definitions with nearby values. -no-pad-sections do not pad the end of sections to alignment boundaries -no-parallel disable -parallel -no-predefined-syms Do not provide mmixal built-in constants. Implies -fixed-special-register-names. -no-warn-explicit-parallel-conflicts do not warn when parallel -no-warn-unmatched-high do not warn about missing low relocs -nocpp ignored -nosched disable scheduling restrictions -o OBJFILE name the object-file output OBJFILE (default a.out) -parallel try to combine instructions in parallel -relax Create linker relaxable code. -s ignored -w ignored -warn-explicit-parallel-conflicts warn when parallel instructions -warn-unmatched-high warn when an (s)high reloc has no matching low reloc -x Do not warn when an operand to GETA, a branch, PUSHJ or JUMP is not known to be within range. The linker will catch any errors. Implies -linker-allocated-gregs. -xauto automagically remove dependency violations (default) -xnone turn off dependency violation checking -xdebug debug dependency violation checker -xdebugn debug dependency violation checker but turn off dependency violation checking -xdebugx debug dependency violation checker and turn on dependency violation checking @FILE read options from FILE %s; *input_line_pointer == '%c' 0x%02x AArch64-specific assembler options: ARM-specific assembler options: Blackfin specific assembler options: FR30 specific command line options: GNU assembler version %s (%s) using BFD version %s. H8300-specific assembler options: M32C specific command line options: M32R specific command line options: MMIX-specific command line options: Meta specific command line options: RL78 specific command line options: RX specific command line options: Score-specific assembler options: V850 options: XSTORMY16 specific command line options: Z8K options: -z8001 generate segmented code -z8002 generate unsegmented code -linkrelax create linker relaxable code branch relocation truncate (0x%x) [-2^9 ~ 2^9-1] branch relocation truncate (0x%x) [-2^19 ~ 2^19-1] branch relocation truncate (0x%x) [-2^9 ~ 2^9-1]!%s does not use a sequence number!samegp reloc against symbol without .prologue: %s".else" without matching ".if"".elseif" after ".else"".elseif" without matching ".if"".endif" without ".if"# Example of `%s' instructions .sect .text _start: # bars register# conflicts length#4 not valid on H8/300.###$DPR_BYTE not supported in this context$DPR_GOT not supported in this context$DPR_HWORD not supported in this context$DPR_WORD not supported in this context$DSBT_INDEX must be used with __c6xabi_DSBT_BASE$DSBT_INDEX not supported in this context$GOT not supported in this context$PCR_OFFSET not supported in this context$dbg and $depc are disabled when DEBUG is off$hi and $lo are disabled when MUL and DIV are off$mb0, $me0, $mb1, and $me1 are disabled when COP is off%%%s() must be outermost term in expression%%hi8 only applies to .byte%d error%d errors%d warning%d warnings%s %s -- `%s'%s -- statement `%s' ignored%s NOP inserted%s `%s' already has an alias `%s'%s argument must be a string%s at operand %d -- `%s'%s directive has no name%s for `%s'%s for instruction '%s'%s instruction does not accept a .b suffix%s instruction, operand %d doesn't match%s is enabled by vle flag%s is not used for the selected target%s may not occupy the delay slot of another branch insn.%s must be %d at operand %d -- `%s'%s must have a constant value%s not disabled by vle flag%s not supported in MIPS16 mode%s offset %d out of range %d to %d%s out of range %d to %d at operand %d -- `%s'%s register same as write-back base%s relocations do not fit in %d byte%s relocations do not fit in %d bytes%s relocations do not fit in %u byte%s relocations do not fit in %u bytes%s second argument cannot be a negative number %d%s section is supported only by GNU and FreeBSD targets%s symbol recursion stopped at second appearance of '%s'%s unsupported%s unsupported as instruction fixup%s without %s%s%d-%s%d expected at operand %d -- `%s'%s, %s, generating bad object file %s, treating warnings as errors%s: attempt to rotate the PC register%s: global symbols not supported in common sections%s: no such section%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?%s: total time in assembly: %ld.%06ld %s: unexpected function type: %d%s: unrecognized processor name%s: would close weakref loop: %s%s:%u: bad return from bfd_install_relocation: %x%u-byte relocation cannot be applied to %u-byte field'%.*s' instruction not at start of execute packet'%.*s' instruction not in a software pipelined loop'%.*s' instruction not supported on this architecture'%.*s' instruction not supported on this functional unit'%.*s' instruction not supported on this functional unit for this architecture'%s' can't be a weak_definition (currently only supported in sections of type coalesced)'%s' can't be a weak_definition (since it is undefined)'%s' is not repeatable. Resulting behavior is undefined.'%s' is only available in DD2.0 or higher.'%s' may not be bundled with other instructions.'%s' previously declared as '%s'.'%s': only the NOP instruction can be issued in parallel on the m32r')' required',' expected'APSR', 'CPSR' or 'SPSR' expected'ASR' required'H' modifier only valid for accumulator registers'L' modifier not valid for this instruction'LSL' or 'ASR' required'LSL' required'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher.'ROR' shift is not permitted'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher.'UXTW' not allowed here'UXTW' required'[' expected'[' expected after PLD mnemonic'[' expected after PLI mnemonic']' expected'||' after predicate'||' not followed by instruction'||^' without previous SPMASK'}' expected at end of 'option' field(PC)+ unpredictable(Requires %s; requested architecture is %s.)(default: no) (default: yes) (plt) is only valid on branch targets*-%s conflicts with the other architecture options, which imply -%s-(PC) unpredictable-- unterminated string--absolute-literals option not supported in this Xtensa configuration--compress-debug-sections=%s is unsupported--compress-debug-sections=zstd: gas is not built with zstd support--density option is ignored--fdpic generate an FDPIC object file --generics is deprecated; use --transform instead--gstabs is not supported for ia64--no-density option is ignored--no-generics is deprecated; use --no-transform instead--no-relax is deprecated; use --no-transform instead--no-underscore is invalid with a.out format--nops needs a numeric argument--pic is invalid for this object format--relax is deprecated; use --transform instead-32 create 32 bit object file -64 create 64 bit object file -EL generate code for a little endian machine -EB generate code for a big endian machine --little-endian-data generate code for a machine having big endian instructions and little endian data. -G may not be used in position-independent code-G may not be used with SVR4 PIC code-G may not be used with abicalls-G n Put data <= n bytes in the small data area -G not supported in this configuration-KPIC generate PIC -V print assembler version number -undeclared-regs ignore application global register usage without appropriate .register directive (default) -no-undeclared-regs force error on application global register usage without appropriate .register directive --dcti-couples-detect warn when an unpredictable DCTI couple is found -q ignored -Qy, -Qn ignored -s ignored -KPIC, -call_shared generate SVR4 position independent code -call_nonpic generate non-PIC code that can operate with DSOs -mvxworks-pic generate VxWorks position independent code -non_shared do not generate code that can operate with DSOs -xgot assume a 32 bit GOT -mpdr, -mno-pdr enable/disable creation of .pdr sections -mshared, -mno-shared disable/enable .cpload optimization for position dependent (non shared) code -mabi=ABI create ABI conformant object file for: -R option not supported on this target.-TSO use Total Store Ordering -PSO use Partial Store Ordering -RMO use Relaxed Memory Ordering -l use 1 word for refs to undefined symbols [default 2] -pic, -k generate position independent code -S turn jbsr into jsr --pcrel never turn PC-relative branches into absolute jumps --register-prefix-optional recognize register names without prefix character --bitwise-or do not treat `|' as a comment character --base-size-default-16 base reg without size is 16 bits --base-size-default-32 base reg without size is 32 bits (default) --disp-size-default-16 displacement with unknown size is 16 bits --disp-size-default-32 displacement with unknown size is 32 bits (default) -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated. -no-mCPU don't generate code specific to CPU. For -mCPU and -no-mCPU, CPU must be one of: -mPIC Mark generated file as using large position independent code -m[no-]%-16s enable/disable %s architecture extension -march=%s is not compatible with the selected ABI-march= set architecture -mcpu= set cpu [default %s] -mcpu= Specify the CPU version -mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat} -mdouble Mark generated file as using double precision FP insns -mdsp generate DSP instructions -mno-dsp do not generate DSP instructions -mdspr2 generate DSP R2 instructions -mno-dspr2 do not generate DSP R2 instructions -mdspr3 generate DSP R3 instructions -mno-dspr3 do not generate DSP R3 instructions -mdword Mark generated file as using a 8-byte stack alignment -me Redirect errors to a file -merrors-to-file -mfar-mode | -mf Use extended addressing -mfdpic Assemble for the FDPIC ABI -mfpr-32 Mark generated file as only using 32 FPRs -mfpr-64 Mark generated file as using all 64 FPRs -mgpr-32 Mark generated file as only using 32 GPRs -mgpr-64 Mark generated file as using all 64 GPRs -mhard-float allow floating-point instructions -msoft-float do not allow floating-point instructions -msingle-float only allow 32-bit floating-point operations -mdouble-float allow 32-bit and 64-bit floating-point operations --[no-]construct-floats [dis]allow floating point values to be constructed --[no-]relax-branch [dis]allow out-of-range branches to be relaxed -mignore-branch-isa accept invalid branches requiring an ISA mode switch -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of: -minsn32 only generate 32-bit microMIPS instructions -mno-insn32 generate all microMIPS instructions -mips1 generate MIPS ISA I instructions -mips2 generate MIPS ISA II instructions -mips3 generate MIPS ISA III instructions -mips4 generate MIPS ISA IV instructions -mips5 generate MIPS ISA V instructions -mips32 generate MIPS32 ISA instructions -mips32r2 generate MIPS32 release 2 ISA instructions -mips32r3 generate MIPS32 release 3 ISA instructions -mips32r5 generate MIPS32 release 5 ISA instructions -mips32r6 generate MIPS32 release 6 ISA instructions -mips64 generate MIPS64 ISA instructions -mips64r2 generate MIPS64 release 2 ISA instructions -mips64r3 generate MIPS64 release 3 ISA instructions -mips64r5 generate MIPS64 release 5 ISA instructions -mips64r6 generate MIPS64 release 6 ISA instructions -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of: -mips16 generate mips16 instructions -no-mips16 do not generate mips16 instructions -mips16 cannot be used with -micromips-mlibrary-pic Mark generated file as using position independent code for libraries -mmcu generate MCU instructions -mno-mcu do not generate MCU instructions -mmedia Mark generated file as using media insns -mmicromips generate microMIPS instructions -mno-micromips do not generate microMIPS instructions -mmicromips cannot be used with -mips16-mmsa generate MSA instructions -mno-msa do not generate MSA instructions -mmt generate MT instructions -mno-mt do not generate MT instructions -mmuladd Mark generated file as using multiply add/subtract insns -mno-dword Mark generated file as using a 4-byte stack alignment -mno-pack Do not allow instructions to be packed -mnopic Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic -mpack Allow instructions to be packed -mpic Mark generated file as using small position independent code -msmartmips generate smartmips instructions -mno-smartmips do not generate smartmips instructions -msoft-float Mark generated file as using software FP -mtomcat-debug Debug tomcat workarounds -mtomcat-stats Print out stats for tomcat workarounds -mvirt generate Virtualization instructions -mno-virt do not generate Virtualization instructions -mxpa generate eXtended Physical Address (XPA) instructions -mno-xpa do not generate eXtended Physical Address (XPA) instructions .%s outside of %s....COMMon length (%d.) < 0! Ignored..COMMon length (%ld.) <0! Ignored..COMMon length (%lu) out of range ignored.EQU must use a label.EXIT must appear within a procedure.REG expression must be a register.REG must use a label.SCOMMon length (%ld.) <0! Ignored..abiversion expression does not evaluate to a constant.abort detected. Abandoning ship..arch requires a matching --march=... option.asmfunc pseudo-op only available with -mccs flag..asmfunc repeated..asmfunc without function..begin [no-]density is ignored.begin directive with no matching .end directive.begin directive without a preceding .ent directive.begin directive without a preceding .file directive.begin literal is deprecated; use .literal instead.begin/.bend in different segments.bend directive names unknown symbol.bend directive without a preceding .ent directive.bend directive without a preceding .file directive.bss size %d < 0!.bss size %ld < 0!.bss size argument missing .bundle_align_mode alignment too large (maximum %u).bundle_lock sequence at %u bytes, but .bundle_align_mode limit is %u bytes.bundle_lock with no matching .bundle_unlock.bundle_unlock without preceding .bundle_lock.callinfo is not within a procedure definition.cfi_endproc without corresponding .cfi_startproc.cfi_fde_data is not supported for this target.cfi_fde_data without corresponding .cfi_startproc.cfi_inline_lsda is not supported for this target.cfi_inline_lsda not valid for this frame.cfi_lsda requires encoding and symbol arguments.cfi_personality requires encoding and symbol arguments.cfi_personality_id is not supported for this target.compiler directive missing language and version.compiler directive missing version.cpload not in noreorder section.def pseudo-op only available with -mccs flag..def pseudo-op used inside of .def/.endef: ignored..def pseudo-op used inside of .def/.endef; ignored.dim pseudo-op used outside of .def/.endef: ignored..dim pseudo-op used outside of .def/.endef; ignored.ef with no preceding .function.end [no-]density is ignored.end directive has no name.end directive missing or unknown symbol.end directive names different symbol than .ent.end directive names unknown symbol.end directive without a preceding .ent directive.end directive without a preceding .ent directive..end directive without a preceding .file directive.end directive without matching .ent.end not in text section.end symbol does not match .ent symbol.end symbol does not match .ent symbol..end%c encountered without preceding %s.end%s without preceding .%s.endasmfunc pseudo-op only available with -mccs flag..endasmfunc without a .asmfunc..endasmfunc without function..endef pseudo-op used before .def; ignored.endef pseudo-op used outside of .def/.endef: ignored..endfunc missing for previous .func.endfunc missing for previous .proc.ent directive has no name.ent directive has no symbol.ent directive without matching .end.ent or .aent not in text section.ent or .aent not in text section..err encountered.error directive invoked in source file.es without preceding .bs.fail %ld encountered.field count '%d' out of range (1 <= X <= 32).fill size clamped to %d.fmask outside of .ent.fnend directive without .fnstart.frame outside of .ent.gnu_attribute %d,%d is incompatible with `%s'.gnu_attribute %d,%d is no longer supported.gnu_attribute %d,%d is not a recognized floating-point ABI.gnu_attribute %d,%d requires `%s'.handler directive has no name.ifeqs syntax error.incbin count zero, ignoring `%s'.inst.n operand too big. Use .inst.w instead.largecomm supported only in 64bit mode, producing .comm.linkonce is not supported for this object file format.literal not allowed inside .begin literal region.literal_position inside literal directive; ignoring.ln pseudo-op inside .def/.endef: ignored..loc before .file.loc outside of .text.loc pseudo-op inside .def/.endef: ignored..localentry expression for `%s' does not evaluate to a constant.localentry expression for `%s' is not a valid power of 2.longcall pseudo-op seen when not relaxing.longjump pseudo-op seen when not relaxing.machine stack overflow.machine stack underflow.machinemode stack overflow.machinemode stack underflow.mask outside of .ent.mask/.fmask outside of .ent.module is not permitted after generating code.module used with unrecognized symbol: %s .name directive has no symbol.name directive not in link (.link) section.option pic%d not supported.option pic%d not supported in VxWorks PIC mode.option pop with no .option push.pdesc directive has no entry symbol.pdesc directive not in link (.link) section.pdesc doesn't match with last .ent.pdesc has a bad entry symbol.popsection without corresponding .pushsection; ignored.previous without corresponding .section; ignored.profiler pseudo requires at least two operands..prologue directive without a preceding .ent directive.prologue within prologue.ref outside .csect.ref pseudo-op only available with -mccs flag..sblock may be used for initialized sections only.scl pseudo-op used outside of .def/.endef: ignored..scl pseudo-op used outside of .def/.endef; ignored.sect: subsection name ignored.set pop with no .set push.set syntax invalid .size expression for %s does not evaluate to a constant.size pseudo-op used outside of .def/.endef: ignored..size pseudo-op used outside of .def/.endef; ignored.space repeat count is negative, ignored.space repeat count is zero, ignored.space/.bes repeat count is negative, ignored.space/.bes repeat count is zero, ignored.stab%c is not supported.stab%c: description field '%x' too big, try a different debug format.stab%c: ignoring non-zero other field.stab%c: missing comma.stabx of storage class stsym must be within .bs/.es.syntax %s requires command-line option `--no-underscore'.syntax %s requires command-line option `--underscore'.tag pseudo-op used outside of .def/.endef: ignored..tag pseudo-op used outside of .def/.endef; ignored.tag requires a structure tag.tag target '%s' undefined.tc not in .toc section.tc with no label.type pseudo-op used outside of .def/.endef: ignored..type pseudo-op used outside of .def/.endef; ignored.unwind_save does not support this kind of register.usect: non-zero alignment flag ignored.usepv directive has no name.usepv directive has no type.uses does not refer to a local symbol in the same section.uses pseudo-op seen when not relaxing.uses target does not refer to a local symbol in the same section.val expression is too complex.val pseudo-op used outside of .def/.endef: ignored..val pseudo-op used outside of .def/.endef; ignored.var may only be used within a macro definition.vframepsp is meaningless, assuming .vframesp was meant.vliw unavailable when VLIW is disabled..warning directive invoked in source file.word %s-%s+%s didn't fit.word case-table handling failed: table too large0x%lx: "%s" type = %ld, class = %d, segment = %d 128-bit-wide accsess not allowed on selected system register '%s'16-bit address isn't allowed in MPX instructions16-bit extension16-bit jump out of range16-bit relocation used in 8-bit operand3-bit immediate out of range32-bit address isn't allowed in 64-bit MPX instructions.32-bit conditional branch generated32bit mode not supported on `%s'.6-bit displacement out of range6-bit immediate out of range62-bit relocation not yet implemented64bit mode not supported on `%s'.68040 and 68851 specified; mmu instructions may assemble incorrectly8-bit displacement out of range8-bit immediate out of range8-bit relocation used in 16-bit operand: Immediate value in cbcond is out of range.: Instruction requires frs2 and frsd must be the same register: PC-relative operand can't be a constant: TLS operand can't be a constant: There are only 32 f registers; [0-31]: There are only 32 single precision f registers; [0-31]: There are only 64 f registers; [0-63]: asr number must be between 0 and 31: crypto immediate must be between 0 and 31: expected register name ccr : expected register name pc : expected register name r0-r7 : expecting %asrN: expecting crypto immediate: imm2 immediate operand out of range (0-3): invalid ASI expression: invalid ASI name: invalid ASI number: invalid cpreg name: invalid membar mask expression: invalid membar mask name: invalid membar mask number: invalid prefetch function expression: invalid prefetch function name: invalid prefetch function number: invalid siam mode expression: invalid siam mode number: non-immdiate imm2 operand: unrecognizable ancillary state register: unrecognizable hyperprivileged register: unrecognizable privileged register:b not permitted; defaulting to :w:lower16: not allowed in this instruction:operand has too many bits:operand value(%d) too big for constraint:unknown relocation constraint size:upper16: not allowed in this instruction specify for ABI Specify a abi version could be v1, v2, v2fp, v2fpp assemble for floating point ABI Assemble for architecture could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s assemble for architecture Assemble for baseline could be v2, v3, v3m assemble for CPU assemble for DSP architecture assemble for FPU architecture Specify a FPU configuration 0: 8 SP / 4 DP registers 1: 16 SP / 8 DP registers 2: 32 SP / 16 DP registers 3: 32 SP / 32 DP registers,X